1) Field of the Invention
This invention relates generally to fabrication of semiconductor memory devices and more particularly to the fabrication of a self aligned floating gate using Shallow trench isolation.
2) Description of the Prior Art
More efficient utilization of device area in VLSI technology is a prominent objective in order to increase the density and number of devices and memory cells on a semiconductor chip. This reduces cost and increase the speed of operation. A known technique is to place various elements, i.e., shallow trench isolation (STI), transistors, capacitors, etch in trenches to achieve greater element density.
A deficiency with current memory devices is the poor quality of the intergate dielectric layers between the floating gate (FG) and the control gate (CG) which causes low breakdown voltages. The inconsistent quality of the intergate dielectric layers worsens as the devices are further shrunk and the intergate dielectric layers are made thinner.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,382,534 (Sheu et al.) shows a method for forming a recessed SID regions. U.S. Pat. No. 5,554,550 (Yang) shows a method for forming a gate in a trench.
However there is still a need for an improved memory cell formation and isolation method.